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SN74ALVCH16270DLR
Opis:
SN74ALVCH16270DLR datasheet pdf and Logic - Universal Bus Functions product details from Rochester Electronics stock available at Rozee
Kategoria:
Obwody zintegrowane
Specyfikacje
Part Number:
SN74ALVCH16270DLR
Manufacturer:
Rochester Electronics
Description:
In stock. Alternative models available.
Lifecycle:
New from this manufacturer
Delivery:
DHL、UPS、FedEx、Registered Mail
Payment:
T/T Paypal Visa Western Union
More Information:
SN74ALVCH16270DLR More Information
ECAD:
Request Free CAD Models
Pricing(USD):
$1.07
Remark:
Manufacturer: Rochester Electronics.
Rozee is one of the Distributors.
Wide range of applications.
Mount:
Surface Mount
Height:
2.79 mm
Weight:
694.790113 mg
Packaging:
Tape and Reel
Case/Package:
SSOP
Number of Bits:
24
Output Current:
24 mA
Number of Outputs:
12
Quiescent Current:
40 µA
Max Supply Voltage:
3.6 V
Number of Circuits:
1
Turn-On Delay Time:
7.2 ns
Nominal Supply Current:
250 mA
Low Level Output Current:
24 mA
Max Operating Temperature:
85 °C
Products Category:
Integrated Circuits (ICs) - Logic - Universal Bus Functions
Qty:
9918 In Stock
Applications:
Test & measurement
Grid infrastructure
Wired networking
Width:
7.49 mm
Length:
18.41 mm
Polarity:
Non-Inverting
Thickness:
2.59 mm
Logic Function:
AND
Number of Pins:
56
Number of Inputs:
12
Propagation Delay:
5.1 ns
Max Supply Current:
40 µA
Min Supply Voltage:
1.65 V
Number of Elements:
1
Number of Input Lines:
12
Number of Output Lines:
24
High Level Output Current:
-24 mA
Min Operating Temperature:
-40 °C
Numer modelu:
SN74ALVCH16270DLR
Wprowadzenie
SN74ALVCH16270DLR Overview\\\\nSN74ALVCH16270DLR is a model belonging to the Logic - Universal Bus Functions subcategory under Integrated Circuits (ICs). For specific product performance parameters, please refer to the data sheet, such as PDF files Docx documents, etc. We have SN74ALVCH16270DLR high-definition pictures and data sheets for reference. We will continue to produce various video files and 3D models for users to understand our product more intuitively and
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